The present invention relates to a method for driving sustain lines for a white balance in a plasma display panel, and more particularly to a method for driving sustain lines in a plasma display panel, in which when the white balance is adjusted considering the characteristic of the panel, an erase pulse is inserted by the color in the period in which the sustain pulse is applied, so that the pulses of a ratio required in good white balance can be applied.
For example, a plasma display device, one of flat panel displays, has a plasma display panel (PDP) of luminous element and displays image sequence or still picture by using the gas discharge phenomenon in the PDP
FIG. 1 shows a cell structure in a general plasma display panel. In the figure, the PDP has an upper glass substrate 1, i.e., the surface on which picture is displayed, a lower glass substrate 2 disposed in parallel with the upper glass substrate 1 by a predetermined distance, a barrier rib 3 arranged between the upper glass substrate 1 and the lower glass substrate 2 to form a discharge space, a scan electrode 4 and a common electrode 5 (hereinafter, referred to as xe2x80x9cfirst and second sustain electrodesxe2x80x9d) alternately arranged on the surface of the upper glass substrate 1 facing the lower glass substrate 2 to be directly crossed with the barrier rib 3, a dielectric layer 6 formed below the surface of the upper glass substrate 1 facing the lower glass substrate 2 to limit the discharge current, an address electrode 7 formed on the surface of the lower glass substrate 2 facing the upper glass substrate 1 between the barrier ribs 3 to generate a discharge together with the first and second sustain electrodes 4 and 5, a phosphor layer 8 which is formed on the lower glass substrate 2, the barrier rib 3 and the address electrode 7 in the discharging space and emits visible light of the phosphor 8 red, green and blue(R, G, B) at the discharge of each cell.
The PDP structured as described above generates the visible light by exciting the phosphor material to the ultraviolet rays emitted at the discharge between the electrodes, and such a discharge will be described with reference to FIGS. 2 and 3.
FIGS. 2 and 3 show the driving wave forms applied to each electrode and the wall charge processing states of corresponding cell according to the driving wave forms.
In embodying the grey level of a picture element, a cathode-ray tube (CRT) can adjust the brightness by using the strength of an electron beam, while the PDP embodies the grey level by the number of discharge per unit time because of the difficulty of adjusting the strength of discharge.
One picture element is composed of three discharge cells of R, G and B. In the case of 256 grey levels, if the discharge number of each cell is divided into 0xcx9c255 every frame, the brightness of 256 grey levels can be embodied according to the discharge number.
The discharges selectively occurred in each cell are composed of an address discharge for addressing a luminous picture element, a sustain discharge for sustaining the discharge of the cell and an erase discharge for stopping the sustaining of the discharge cell.
Here, the wall charge is formed on the dielectric layer 6 near the first and second sustain electrodes 4 and 5 in the discharge space by the address discharge between the address electrode 7 of the lower glass substrate 2 and the sustain electrodes 4 and 5 of the upper glass substrate 1, and is sustained by the sustain discharge between the first and second sustain electrodes 4 and 5 of the upper glass substrate 1.
If the driving wave forms shown in FIG. 2 are applied to the electrodes 4, 5 and 7, the processing states of the wall charge in the sections (a) to (h) are shown as states (a) to (h) in FIG. 3.
That is, there was no wall charge in the discharge cell before the state (a) of FIG. 3. If there occurs an address discharge between the address electrode 7 and the first sustain electrode 4 in the section (a), there forms the wall charge in the cell at the section (b) after the address discharge.
In this case, most of the wall charge are formed at the first and second sustain electrodes 4 and 5. The write pulse applied to the address electrode 7 has a width of over 2 xcexcs and this width corresponds to the time required in forming the wall charge.
There occurs the sustain discharge between the first and second sustain electrodes 4 and 5 at the section (c), and after the sustain discharge, the wall charge opposite to that at the section (b) is formed at the section (d).
In this case, the sustain voltage of the electrodes 4, 5 and 7 may be lower than the difference of the write voltage between the address electrode 7 and the sustain electrode 4. This is because of the wall charge formed on the dielectric layer 6 and there occurs no sustain discharge at the cell having no wall charge.
At the sections (e) and (f), there occurs a sustain discharge by the sustain pulse and the wall charge opposite to that at the section (d) is formed.
Hence, one sustain period is from the section (c) to the section (f), and the discharge number during one sustain period is 2.
The erase discharge occurs at the section (g) of FIG. 3 by the erase pulse of FIG. 2. And the erase pulse has a width of less than 1 xcexcs and the voltage of the erase pulse is lower than that of the sustain pulse. There occurs a discharge between the first and second sustain electrodes 4 and 5 by this erase pulse, but the cell has no wall charge at the section (h) because there was no time to form the wall charge, and thus there occurs no discharge even though the sustain pulse is applied.
FIG. 4 shows a driving circuit of a general plasma display panel. The driving circuit comprises a PDP 10 having 640 R, G and B address electrode lines (R1, G1, B1, . . . R640, G640, B640) and 480 first and second sustain electrode lines (S1, S2, S479, S480), a microprocessor 20 of digitalizing the R, G and B picture data applied from the exterior and outputting R, G and B digital picture data of 8 bits (2s=256 grey levels) and various control signals required in driving the PDP 10 according to the external signal, a scanning and sustain driver 30 for applying a scan pulse to the first and second sustain electrode lines (S1xcx9cS480) according to the control of the microprocessor 20 to sequentially scan the lines and applying the sustain pulse to all of the first and second sustain electrode lines (S1xcx9cS480) to sustain the discharge and luminescence of each cell, a memory 40 for storing the R, G and B digital picture data of the microprocessor 20 by the frame, the color and the bit, and an address driver 50 for reading the bit values of 640 R, G and B digital picture data corresponding to the first and second sustain electrode lines S1xcx9cS480 from the memory 40 by the scanning of the scanning and sustain driver 30 and applying the bit values to 640 R, G and B address electrode lines R1xcx9cB640.
The scanning and sustain driver 30 has a clock and data generator 31 for generating a clock CLK and data according to the control of the microprocessor 20, a sustain pulse generator 32 for generating the sustain pulse according to the control of the microprocessor 20, and a driving logic unit 33 for sequentially applying the scan pulse and the sustain pulse to the first and second sustain electrode lines S1xcx9cS480 according to the clock, data and sustain pulse.
A description will be made on the process of displaying picture of 256 grey levels on the panel according to an address-display-separating (ADS) sub-field method with reference to FIGS. 1 to 3.
In the ADS sub-field method, for the embodiment of 2s grey levels, 1 frame of screen is displayed by being divided into X sub-field screens and the picture data applied from the exterior are digitalized into X bits of digital picture data (least significant bit(D1)xcx9cmost significant bit(DX)) to apply them to the panel.
Each sub-field screen is composed of a reset period, an address period and a sustain period. The reset period and address period are equally allotted every sub-field, while the sustain period is varied according to the bit weight of the digital picture data displayed at the address period, such that the grey level of picture can be embodied by the combination of each sub-field.
That is, one frame is divided into 8 sub-fields (SF1xcx9cSF8) and the sustain period of each sub-field is allotted in the ratio of 20:21:22: . . . 2Xxe2x88x922:2xe2x88x921.
Hence, for the embodiment of 256 grey levels, the microprocessor 20 digitalizes R, G and B analog picture signals and outputs 8 bits of R, G and B digital picture data and various control signals required in driving the PDP 10 according to the external signal.
The R, G and B digital picture data output from the microprocessor 20 is stored at the memory 40 by the frame, color and bit.
Thereafter, in the reset and address periods of the sub-field(SF1xcx9cSF8), the driving logic unit 33 applies to the first and second sustain electrode lines S1xcx9cS480 the erase pulse for erasing the wall charge formed at the previous field in the first step, the write pulse for forming uniform wall charge on the whole of the panel 10 in the second step and the erase pulse in the third step and forms the wall charge on 640 R, G and B address electrode lines R1xcx9cB640. Thereby, the address discharge voltage applied thereafter becomes lowered.
In the fourth step, the scan pulse is sequentially applied to the first and second sustain electrode lines S1xcx9cS480 according to the clock, data synchronized thereto and the sustain pulse and then, the scanning of the first and second sustain electrode lines S1xcx9cS480 is completed.
When the scan pulse is applied in the fourth step, the address driver 50 synchronizes the address pulse (one bit value of R, G and B digital picture data) corresponding to the first and second sustain electrode lines (S1xcx9cS480) with the scan pulse and applies it to each of the address electrode lines R1xcx9cB640, and thereby there occurs a discharge in the discharge space of each cell.
The address driver 50 applies 8 bits of R, G and B digital picture data D1xcx9cD8 corresponding to each cell to the sub-field SF1xcx9cSF8, respectively.
In the meanwhile, if the address period of each sub-field SF1xcx9cSF1 is completed, the driving logic unit 33 receives the sustain pulse from the sustain pulse generator 32 and applies the sustain pulse the number of which is in proportion to SF1:SF1: . . . SF8:SF8=20:21: . . . 26:27 to all of the sustain electrode lines S1xcx9cS480. Thereby, the discharge and luminescence of same cells which have been discharged in the address period are sustained in the sustain period.
If the construction of the sub-field SF1xcx9cSF8 is completed with the repetition of such a process, the picture of 256 grey levels is displayed on the PDP 10.
In the above described plasma display panel driving method, R, G and B are sustained together, and thus it is impossible to adjust the white balance by the number of the sustain pulses.
To solve such a problem, a lookup table is used in the driving circuit of the plasma display panel and thus the white balance is adjusted by the change of data or by the change of the phosphor material.
However, in the case of using the lookup table, it has a problem that the color which can be displayed is reduced by the reduction of gray level and an additional cost is required in using the lookup table.
In the case of changing the phosphor material, it is difficult to adjust minute white balance and further to adjust correct brightness ratio of R, G and B by the change of the driving voltage due to the difference of each set, i.e., the difference of the doping thickness of the phosphor material or the difference of the electrode.
Accordingly, it is preferred that a PDP of low cost, high reliability and stable picture quality is applied while solving the above problems.
Accordingly, an object of the present invention is to apply a method of driving sustain lines in a plasma display panel, which can correctly adjust the white balance by independently adjusting the sustain pulse.
Another object of the present invention is to apply a method of independently adjusting the ratio of color by applying the erase pulse to the scan electrode and address electrode or the common electrode and address electrode by the color.
To achieve the above objects of the present invention, there is applied a method for driving sustain lines in a plasma display panel. The method has the steps of measuring the brightness of each color signal and the color coordinates from at least more than one sub-field and calculating the number of the sustain pulses of the color signal ratio required in good white balance; applying the sustain pulse to the scan electrode and the common electrode after calculating the number of the sustain pulses; applying an erase pulse of a predetermined width to the scan electrode and the address electrode by the color based on the calculated value for the period in which the sustain pulse is applied; and independently adjusting the sustain period of each color signal based on the erase pulse by the color,
Selectively, the erase pulses by the color applied to the scan electrode and the address electrode have the same pulse width and inverted phase from each other.
Selectively, the width of the erase pulse is in the range of 0.5 to 1.2 xcexcs.
Selectively, at lease two pairs of the erase pulses by the color are applied to independently adjust the sustain periods of at least two colors, thus adjusting the ratio of the color signals.
The sustain line driving method of the plasma display panel according to another preferred embodiment of the present invention has the steps of measuring the brightness of each color signal and the color coordinates from at least more than one sub-field and calculating the number of the sustain pulses of the color signal ratio required in good white balance; applying the sustain pulse to the scan electrode and the common electrode after calculating the number of the sustain pulses; applying an erase pulse of a predetermined width to the address electrode and the common electrode by the color based on the calculated value for the period in which the sustain pulse is applied; and independently adjusting the sustain period of each color signal based on the erase pulse by the color.
Selectively, the erase pulses by the color applied to the address electrode and the common electrode have the same pulse width and inverted phase from each other.
As described above, the brightness and color coordinates of each of R, G and B are measured every sub-field and the erase pulse is applied, based on the number of the sustain pulses of the ratio required in good white balance.
As a result, it is possible to correctly adjust the white balance without adding the lookup table or changing the phosphor material in the plasma display panel.